1. Field of the Invention
The present invention relates to an active matrix substrate wherein each pixel, which is formed in a matrix, is driven by a switching element provided for each pixel. The present invention further relates to a method for producing such an active matrix substrate.
2. Description of the Related Art
In recent years, the size and weight of OA (Office Automation) apparatuses, such as personal computers and the like, have decreased, and commercial use of personal portable information apparatuses, or the like, has advanced. In such portable information apparatuses, a liquid crystal display (LCD) is most frequently used as a display device because of its small consumption of electric power, small size, and light weight.
In recent years, an even higher increase in the display quality of a LCD is in demand. Accordingly, an LCD based on an active matrix substrate having switching elements, each of which is provided to a respective pixel, has been widely used.
FIG. 35 is a schematic view showing a basic structure of an active matrix substrate 1 which is used in a liquid crystal display device.
The active matrix substrate 1 includes a plurality of scan lines 2 and a plurality of signal lines 3, which cross each other at right angle. Each of the scan lines 2 and each of the signal lines 3 are connected to a scan line driving circuit 4 and a signal line driving circuit 5, respectively. In each of the regions defined by the scan lines 2 and signal lines 3, a pixel 6 is formed, which is a minimum display unit for displaying an image on a display region. For each pixel 6, a thin film transistor (TFT) 7 is formed as a switching element at each intersection of the scan lines 2 and signal lines 3. A plurality of such pixels 6 are formed in a matrix over the active matrix substrate 1, so that the entire surface of the active matrix substrate 1 acts as a display region.
FIG. 36 shows an enlarged view of one of the pixels 6 of the active matrix substrate 1 shown in FIG. 35. Each scan line 2 is connected to a gate electrode 7a of the TFT 7, and each signal line 3 is connected to a source electrode 7b of the TFT 7. A drain electrode 7c of the TFT 7 is connected to a pixel electrode 8, which is provided to each pixel 6.
When the active matrix substrate 1 having the above structure is driven, the scan line driving circuit 4 applies a scan voltage to each of the plurality of scan lines 2 in a line-sequential manner. In response to application of the scan voltage, the gate electrode 7a of the TFT 7, which is connected to the scan line 2 to which the scan voltage is applied, turns on the conductive state between the source electrode 7b and the drain electrode 7c. The signal line driving circuit 5 applies a pixel voltage to each signal line 3 in synchronization with application of the scan voltage to the scan line 2, so as to write an image signal in the pixel electrode 8 of each of the pixel 6 which are in the on-state due to the application of the scan voltage.
Such an active matrix substrate 1, for example, an active matrix substrate as disclosed in Japanese Laid-Open Publication No. 11-119261, is known.
FIG. 37 is an enlarged plan view showing one of the pixels of the active matrix substrate 1. FIG. 38 is a cross-sectional view taken along line A-A′ of FIG. 37.
The active matrix substrate 1 shown in FIG. 37 has a plurality of scan lines 2 over a transparent insulative substrate 11, such as glass, so as to be parallel to each other with a predetermined interval. At substantially a central portion between adjacent scan lines 2, an auxiliary capacitive line 12 is provided parallel to the scan lines 2. A gate electrode 7a of a TFT 7, which is formed for each pixel 6, is connected to the scan line 2. Over the entire surface of the transparent insulative substrate 11 including the scan lines 2, the signal lines 3, and the gate electrode 7a of the TFT 7, a gate insulating film 13 is formed. A semiconductor layer 14 is formed on a portion of the gate insulating film 13 which is above the gate electrode 7a. On a central portion of the semiconductor layer 14, a channel protecting layer 15 is formed. A source electrode 7b and drain electrode 7c formed of an n+ Si layer are provided so as to cover edges of the semiconductor layer 14 and the channel protecting layer 15.
On the gate insulating film 13, signal lines 3 are formed at predetermined intervals so as to cross each scan line 2 at right angles. Each signal line 3 has a two-layered structure including a transparent electrode layer 3a and a metal layer 3b, and is connected to the source electrode 7b of the TFT 7. On the other hand, the drain electrode 7c is connected to a connection electrode 16. The connection electrode 16 is connected to a pixel electrode 8 which writes a pixel voltage. The connection electrode 16 extends to a central portion of the pixel 6 where the auxiliary capacitive line 12 is formed, and is patterned so as to run along the auxiliary capacitive line 12.
An interlayer insulating film 17 is formed on the TFT 7, the connection electrode 16, the scan line 2, and the signal line 3. In the interlayer insulating film 17, a contact hole 18 is formed above the auxiliary capacitive line 12 so as to reach the connection electrode 16. Over the interlayer insulating film 17, the pixel electrode 8 is formed over the entire region of each pixel 6 so as to be in electrical contact with the connection electrode 16 through the contact hole 18.
In the above-described active matrix substrate 1 of the conventional liquid crystal display device, the transparent insulative substrate 11 is typically made of a glass substrate. However, the glass substrate is heavy and easily broken when dropped to the ground, for example. Thus, such a glass substrate is not fit for use in a light-weighted portable information apparatus which is required to be deformation-resistant and to be not easily broken upon impact on the ground or the like.
Therefore, plastic has been receiving attention as a material for the transparent insulative substrate 11 which is light weight and is deformation- and shock-resistant. Research has been carried out for using plastic as a material of the transparent insulative substrate 11 of the active matrix substrate 1.
However, a plastic substrate differs from a glass substrate in that the size of the plastic substrate largely varies in accordance with its environment during a production process. For example, the glass substrate has a variation rate against temperature of 3 to 5 ppm/° C., while the plastic substrate has a variation rate against temperature of 50 to 100 ppm/° C. Further, the size of the plastic substrate varies when it absorbs moisture. The variation rate in a size of the plastic substrate is about 3000 ppm. Thus, when such a plastic substrate is used, it is necessary to determine the structure of each component of the active matrix substrate in consideration of such variations in size which may be caused by environmental variations.
A conventional substrate made of plastic will now be described with reference to FIG. 39. FIG. 39 is an enlarged plan view showing one of the pixels of the active matrix substrate 1 which is formed on the transparent insulative substrate 11 made of plastic. Section (a) shows a pixel of an active matrix substrate in which an auxiliary capacitive line 12 is formed. Section (b) shows a pixel of an active matrix substrate in which an auxiliary capacitive line 12 is not formed.
In FIG. 40, sections (a) through (f) illustrate steps of a method for producing the active matrix substrate 1 shown in section (a) of FIG. 39.
The method for producing the active matrix substrate 1 shown in section (a) of FIG. 39, in which variations in the size of the transparent insulative substrate 11 made of plastic are considered, is described with reference to FIGS. 40 through 42.
In the first step, as shown in section (a) of FIG. 40, on the transparent insulative substrate 11 made of transparent plastic, scan lines 2 and an auxiliary capacitive line 12 are formed of opaque metal so as to be in parallel to each other.
Next, a gate insulating film 13 is formed over the entire structure of the insulative substrate 11. On the gate insulating film 13, an amorphous Si layer 21 and an n+ amorphous Si layer 22, which will be formed into a source electrode 7a and a drain electrode 7b in a subsequent step, are formed (see FIG. 41). Then, a positive-type photoresist is formed on the n+ amorphous Si layer 22 and patterned by exposing both the upper and lower surfaces of the structure to light, such that the photoresist is left only on the scan lines 2. The resultant structure is etched using this photoresist as a mask so as to form a stripe pattern of the amorphous Si layer 21 and the n+ amorphous Si layer 22 on the scan lines 2 as shown in section (b) of FIG. 40. FIG. 41 is a cross-sectional view taken along line B-B′ of section (b) of FIG. 40. FIG. 41 shows the amorphous Si layer 21 and the n+ amorphous Si layer 22, which are formed on the scan lines 2 and which run along the scan lines 2.
Next, signal lines 3 and a connection electrode 16 are patterned as shown in section (c) of FIG. 40.
In FIG. 42, sections (a) through (c) are cross-sectional views taken along line C-C′ of section (c) of FIG. 40, which illustrate steps of forming the signal lines 3 and the connection electrode 16 patterned as shown in section (c) of FIG. 40.
In this case, in the first place, as shown in section (a) of FIG. 42, a transparent electrode layer 23 of a light-permeable, electrically-conductive material such as ITO, which will be a lower electrode layer of the signal lines 3 and a connection electrode 16, and an opaque electrode layer 24 of an light-impermeable, electrically-conductive material, which will be an upper electrode layer of the signal lines 3 and a connection electrode 16, are sequentially formed. Thereafter, a photoresist layer 25 is formed for patterning the signal lines 3 and a connection electrode 16.
The photoresist layer 25 formed on the opaque electrode layer 24 has a portion which has been partially exposed to light as shown in section (a) of FIG. 42 (half exposure portion 25a), which will be a channel portion of the TFT. The half exposure portion 25a is formed through a half exposure process where a half-tone mask or a slit-shaped mask is used to insufficiently expose a corresponding portion of the photoresist 25, such that the insufficiently-exposed portion (i.e., half exposure portion 25a) becomes thinner than the other portions of the photoresist 25. After such a photoresist 25 has been formed, the photoresist 25 is used as a mask so as to etch away unmasked portions of the opaque electrode layer 24, the transparent electrode layer 23, the n+ amorphous Si layer 22, and the amorphous Si layer 21 as shown in section (b) of FIG. 42. Then, the resist in the half exposure portion 25a is removed, and portions of the opaque electrode layer 24, the transparent electrode layer 23, and the n+ amorphous Si layer 22 in the half exposure portion 25a are etched away so as to form a source electrode 7b and a drain electrode 7c on the amorphous Si layer 21 as shown in section (c) of FIG. 42.
In this example, in the active matrix substrate 1, the signal lines 3 and a connection electrode 16 each have a two-layered structure including the transparent electrode layer 23 made of ITO, or the like, and the opaque electrode layer 24. However, the signal lines 3 and a connection electrode 16 may be formed by only the opaque electrode layer 24.
According to the above method, the TFT 7, which functions as a switching element, can be accurately formed even when a displacement is caused in the alignment of the patterns of the signal lines 3, the source electrode 7b of the TFT 7, and the drain electrode 7c of the TFT 7, with respect to the pattern of the scan lines 2, due to extension and contraction of the insulative substrate 11 which may occur after formation of the scan lines 2.
Next, a TFT protection film 26 (FIG. 43) of SiNx or the like is formed over the entire upper surface of the insulative substrate 11. On the TFT protection film 26, an interlayer insulating film 17 is formed of a photosensitive organic resin material so as to cover the entire resultant structure.
In the active matrix substrate 1, a two-layered structure including the TFT protection film 26 of SiNx and the interlayer insulating film 17 of an organic resin material is formed on the signal line 3 or the like. However, only an inorganic layer of SiNx, or the like, may be formed on the signal line 3.
Next, a contact hole 18 is formed in the interlayer insulating film 17 above the auxiliary capacitive line 12 so as to reach the TFT protection film 26 as shown in section (d) of FIG. 40. Then, the interlayer insulating film 17 is used as a mask to etch the TFT protection film 26 in the contact hole 18.
FIG. 43 is a cross-sectional view taken along line D-D′ of section (d) of FIG. 40. FIG. 43 shows a structure where the contact hole 18 formed in the interlayer insulating film 17 reaches the connection electrode 16 beneath the TFT protection film 26.
Next, a transparent electrode layer of ITO or the like, which will be a pixel electrode 8, is formed by sputtering. On this transparent electrode layer, a photoresist layer is formed for patterning the pixel electrode 8, and the photoresist layer is formed into a predetermined pattern through an exposure step.
If the transparent insulative substrate 11 made of plastic is subjected to a normal exposure step, a change in size of the transparent insulative substrate 11 is caused so that the pixel electrode 8 cannot be formed at a desired position. Thus, in the case of the transparent insulative substrate 11 made of plastic, a negative-type photoresist is used to expose the lower surface of the transparent insulative substrate 11 (on which the pixel electrode 8 is not formed) such that the resist layer is left only in regions where the scan lines 2 and the signal lines 3 are not formed, and accordingly, light is transmitted therethrough. (Hereinafter, an exposure process achieved by emitting light from a lower side of the transparent insulative substrate 11 is referred to as a “back surface exposure” process.) In this way, the pattern of the resist layer for forming the pixel electrode 8 is formed. However, in this case where only the exposure of the lower surface is performed, the resist layer is not left in a region over the connection electrode 16 where the contact hole 18 is to be formed. Thus, after the exposure of the lower surface of the transparent insulative substrate 11, the resulting structure is exposed to light from the upper surface side of the transparent insulative substrate 11 so that the resist layer is left in region E shown in section (e) of FIG. 40. (Hereinafter, an exposure process achieved by emitting light from an upper side of the transparent insulative substrate 11 is referred to as a “front surface exposure” process.)
Next, the thus-formed resist layer is used as a mask to pattern the transparent electrode layer made of ITO, or the like, into a desired shape so as to form a pixel electrode 8 for each pixel 6 as shown in section (f) of FIG. 40.
FIG. 44 shows the pixel electrode 8 formed by using the above photoresist. As described above, the pixel electrode 8 is formed for each pixel 6 using the photoresist pattern (indicated by slanted lines in FIG. 44), which is formed by exposure with light from the upper and lower sides of the resulting structure.
FIG. 45 is a cross-sectional view taken along line F-F′ of section (f) of FIG. 40. FIG. 45 shows a structure where the pixel electrode 8 formed on the interlayer insulating film 17 is electrically connected to the opaque electrode layer 24 of the connection electrode 16 through the contact hole 18. FIG. 46 is a cross-sectional view taken along line G-G′ of section (f) of FIG. 40. FIG. 46 shows that the pixel electrode 8 is formed on the inter layer insulating film 17 for each pixel 6.
According to the conventional production method described above, the active matrix substrate 1 wherein the pixel electrode 8 is formed on the interlayer insulating film 17 is completed.
In the active matrix substrate 1 described above, the connection electrode 16 is formed on the auxiliary capacitive line 12, and a portion of the connection electrode 16 also functions as an electrode for the auxiliary capacitance. However, as shown in section (b) of FIG. 39, the active matrix substrate 1 in which the auxiliary capacitive line 12 is not formed, and the connection electrode 16 does not form a part of the auxiliary capacitance may be produced.
In the case where an insulative substrate made of a material having flexibility, such as plastic or the like, is used as the insulative substrate 11 of the active matrix substrate 1, the exposure area, in which a photoresist layer is formed for forming the contact hole 18, the connection electrode 16, and the pixel electrode 8 by etching, is restricted. Hereinafter, this restriction is described with reference to sections (a) and (b) of FIG. 39. In the following description, the maximum amount of displacement between a position where the pattern of an electrode structure is to be formed through the exposure step and a position where the pattern is actually formed through the exposure step, which is cause due to an extension/contraction of the plastic insulative substrate 11 is represented by “Δ”. A maximum amount of displacement, “Δ”, which the position of the electrode structure can have and still operate as intended, is referred to as an “alignment margin”. For example, in the pixel structure shown in section (a) of FIG. 39, the following three types of alignment margins (1) to (3) must be considered.
(1) The contact hole 18 must be formed on the connection electrode 16 so as to electrically connect the pixel electrode 8 to the connection electrode 16. Thus, the pattern of the connection electrode 16 requires an alignment margin greater than 2Δ in all directions, while the contact hole 18 requires an alignment margin of Δ.
(2) The photoresist layer used for forming the pixel electrode 8 must be formed by back surface exposure and front surface exposure which is performed for compensating for the back surface exposure so as to form the photoresist layer over the connection electrode 16. In order to form the pixel electrode 8 using such a photoresist layer as a mask such that the pixel electrode 8 is connected to the connection electrode 16 through the contact hole 18, the exposure pattern used for the front surface exposure must have an alignment margin of 2Δ from at least one of the opposite edges of the connection electrode 16.
Further, when the auxiliary capacitive line 12 and the like are formed in the central region of the pixel 6, and the pixel electrode 8 is divided by the auxiliary capacitive line 12 and the like, as shown in section (a) of FIG. 39, each of the divided regions requires an alignment margin greater than that of the connection electrode 16 by 2Δ. It should be noted that, when a connection electrode 16 is not formed on the auxiliary capacitive line 12 as shown in section (b) of FIG. 39, it is not necessary to consider such an alignment margin.
(3) The resist pattern which is formed by the back surface exposure is used as a mask for forming the pixel electrodes 8 between the signal lines 3 such that adjacent pixel electrodes 8 are divided by a signal line 3 therebetween. However, if the exposure pattern is formed by the front surface exposure so as to be superposed on the signal lines 3, the pixel electrodes 8 cannot be formed separately between adjacent pixels 6. Thus, when front surface exposure is performed, it is necessary to consider an alignment margin of 2Δ between the signal lines 3 and the exposure pattern formed therebetween.
When the above alignment margins (1)-(3) are considered, in order to produce an active matrix substrate using the insulative substrate 11 made of plastic, the photoresist layer, which is exposed for forming the contact hole 18, the connection electrode 16, and the pixel electrode 8, need to be formed with an alignment margin equal to or greater than at least 8Δ in a direction along the width of the pixel electrode 8 (i.e., a pitch of the signal lines 3) as shown in sections (a) and (b) of FIG. 39. Specifically, for example, in the case where the photoresist pattern used for forming the contact hole 18 requires an alignment margin Δ of 20 μm, the pitch of the signal lines 3 cannot be made smaller than about 160 μm (8Δ) at the minimum.
In recent years, there has been demand for pixels to be formed at higher density. Specifically, a pitch of about 50 to 100 μm is required as a size of a pixel electrode. Thus, a decrease in the pitch between signal lines is essential in producing an active matrix substrate using an insulative substrate 11 having flexibility, such as a plastic substrate, so as to have pixel electrodes formed at higher density.